This invention relates to a method of manufacturing a semiconductor device, and more particularly, to a lithography technology capable of forming, at a sufficiently depth and with high accuracy, a pattern alignment mark required at the subsequent step in an element having a mesa.
In gallium arsenide (GaAs) devices such as HEMT, etc. of semiconductor devices, an electron supply layer is formed as an epitaxial layer on a gallium arsenide wafer. For this reason, in forming a device, in order to isolate the electron supply layer, it is necessary to remove unwanted regions to form an epitaxial layer (island) in the form of mesa.
Furthermore, ordinarily, at the time of the removal process step of the unwanted region (hereinafter referred to as an isolation region), an alignment mark necessary for a subsequent patterning process step is formed at the same time.
FIGS. 1A to 1C are device cross sections for every process step for explaining an example of a conventional manufacturing method in a gallium arsenide device, respectively. In this manufacturing method, an alignment mark is formed at the same time in removing the isolation region of the electron supply layer.
Initially, as shown in FIG. 1A, a GaAs substrate 3 on which a buffer GaAs layer 2 and an epitaxial layer 1 are formed is prepared. In this case, as the epitaxial layer 1, a composite layer in which N.sup.+ -GaAs, N-AlGaAs and undope AlGaAs, etc. are epitaxially grown in succession is ordinarily used.
Then, as shown in FIG. 1B, after a resist 4 is coated on the entire surface, a well known technology is used to open an element section electron supply unwanted portion 5 and an alignment mark portion 6. Thereafter, as shown in FIG. 1C, a desired etching is carried out by using the opened resist 4 as a mask to partially remove by etching the epitaxial layer 1 and the buffer GaAs layer 2 at the opened portions to thus form isolation regions 7 and an alignment mark portion 8 at the same time.
In the manufacturing method shown in FIGS. 1A to 1C, the thickness of the epitaxial layer 1 is ordinarily 1000 angstroms or less, and the depth of the etched portion finally formed is 1000 to 2000 angstroms. Thus, a step having a depth of 1000 to 2000 angstroms in a form such that the buffer GaAs layer 2 is partially etched is provided.
FIGS. 2A to 2E show the configuration of a HEMT element made up by the conventional manufacturing method, wherein FIG. 2A is a plan view thereof, and FIGS. 2B and 2C are cross sectional views cut along the lines of X1-X2 and Y1-Y2 of FIG. 2A.
Reference numerals 11 and 12 represent ohmic electrodes and a gate electrode, respectively. At the portions indicated by reference symbols (A) and (B), the gate metal is formed on a step produced by etching of the isolation region. Ordinarily, the thickness of the gate metal is about 3000 to 5000 angstroms and the gate length is 0.25 .mu.m or less. This gate metal portion is of a structure extruded from the island. Accordingly, for example, at the portion of (A), if the step becomes large, there takes place a step break of the gate electrode 12 as shown in FIG. 2D or a peeling or separation as shown in FIG. 2E. For this reason, there arises the problem that the element characteristic becomes poor, etc.
As a measure for this problem, development of the T-shaped gate, etc. is carried out. However, since the portion in contact with the underlying semiconductor substrate is 0.25 .mu.m or less, it is impossible to allow the state where there is not a defect such as peeling, etc. by any means to result.
Accordingly, there is limit in depth of the step, so that value cannot be above a fixed value. In this respect, in accordance with the manufacturing method shown in FIG. 1, the step of alignment mark and the step of the isolation region have the same depth. Since that depth of the step is ordinarily 1000 to 2000 angstroms, in the case of a manual mask alignment by visual observation, a pattern alignment at the next process step can be sufficiently carried out by making use of such a step structure. However, in accordance with an automatic alignment system using reflection of a laser light of He-Ne, etc. to detect alignment mark coordinates, mark detection cannot be made by making use of a step having such a depth because of an insufficient output from a reflected light.
For this reason, there takes place the necessity of increasing the depth of the step of the alignment mark. However, with the method of FIG. 1A to 1C, the depth of the step of the isolation region also becomes large, resulting in the previously described peeling of the gate metal, or the like.
Accordingly, it is required to deepen only the step of the alignment mark without changing the depth of the step of the isolation region.
FIGS. 3A to 3E are device cross sections every process steps showing another manufacturing method conventionally proposed. This manufacturing method is characterized in that it comprises initially forming an alignment mark, and thereafter removing unwanted portions.
The process step shown in FIG. 3A is the same as that shown in FIG. 1A. After a resist 4 is coated as shown in FIG. 3B, an alignment mark portion 6 is first opened. Then, as shown in FIG. 3C, by using the resist 4 as a mask, etching of the opened portion is carried out to form a mark portion 8. Thereafter, as shown in FIG. 3D, a resist 9 is coated for a second time to carry out opening of an element section electron supply unwanted portion 5. Finally, as shown in FIG. 3E, by using the resist 9 as a mask, etching of the unwanted portions is carried out to form an unwanted portion 7.
Since etching of the alignment mark and etching of the unwanted portion are separately carried out, it is possible to freely select the depth of the step. Furthermore, since the step of the alignment mark portion 8 can be large, processing can be sufficiently carried out even by the automatic alignment system.
With this method, however, not only the lithographic process step is disadvantageously increased by one, but also it is required to allow for an alignment deviation because there results, from the process steps subsequent thereto, an indirect alignment with a pattern from which the unwanted portions are removed. Namely, there takes place the necessity of taking into account a deviation of 3.sigma..+-.0.5 .mu.m or less at the time of design.